DIGITAL MICROELEKCTRONIC CIRCUIT DESIGN

AIM

At the end of this class, students will understand the impact of digital circuit design choices on speed, power, and cost. In addition, students will be able to make appropriate trade-offs, using back-of-the-envelope circuit analysis. They will be familiar with options for designing interconnect, data-paths, and specialpurpose digital circuits. They will be able to apply modern design methods and use industry-standard tools. They will be able to design a digital integrated circuit from specification, verify their design, and provide oral and written reports on their work.

CONTENT

This course contains; Course Overview – Introduction,Circuits and Layout,CMOS transistor theory,DC response of CMOS gates,Transient response of CMOS gates,Logical effort theory,Logical effort theory,Power analysis of CMOS circuits,CMOS Sequential Circuits,Interconnect analysis and engineering,Adder architectures and design,Standard cell/gate design,Datapaths,Other circuit families.

1. 1

   1. Circuits and layout 2. CMOS transistor theory, non-ideal transistor characteristics 3. DC and transient response of digital circuits 4. Logical effort theory 5. Power analysis of digital circuits 6. Combinational circuit elements design in CMOS technology 7. Sequential circuit elements design in CMOS technology 8. Interconnects 9. Adder/subtractor circuits 10. Datapaths

   Taught by: Experimental Technique, Project Based Learning Model, Simulation Technique, Lecture Method · Assessed by: Traditional Written Exam, Homework, Project Task

WEEKLY PLAN

1. WEEK 1

   Course Overview – Introduction

   Preparation: Lecture Notes, Related Book Chapter

2. WEEK 2

   Circuits and Layout

   Preparation: Lecture Notes, Related Book Chapter

3. WEEK 3

   CMOS transistor theory

   Preparation: Lecture Notes, Related Book Chapter

4. WEEK 4

   DC response of CMOS gates

   Preparation: Lecture Notes, Related Book Chapter

5. WEEK 5

   Transient response of CMOS gates

   Preparation: Lecture Notes, Related Book Chapter

6. WEEK 6

   Logical effort theory

   Preparation: Lecture Notes, Related Book Chapter

7. WEEK 7

   Logical effort theory

   Preparation: Lecture Notes, Related Book Chapter

8. WEEK 8

   Power analysis of CMOS circuits

   Preparation: Lecture Notes, Related Book Chapter

9. WEEK 9

   CMOS Sequential Circuits

   Preparation: Lecture Notes, Related Book Chapter

10. WEEK 10

    Interconnect analysis and engineering

    Preparation: Lecture Notes, Related Book Chapter

11. WEEK 11

    Adder architectures and design

    Preparation: Lecture Notes, Related Book Chapter

12. WEEK 12

    Standard cell/gate design

    Preparation: Lecture Notes, Related Book Chapter

13. WEEK 13

    Datapaths

    Preparation: Lecture Notes, Related Book Chapter

14. WEEK 14

    Other circuit families

    Preparation: Lecture Notes, Related Book Chapter

ASSESSMENT

• Rate of Midterm Exam to Success30%
• Rate of Final Exam to Success70%

WORKLOAD

READING

• Textbook: Integrated Circuit Design, 4th Ed., (Weste& Harris, Addison Wesley, 2011) Tools: Cadence Virtuoso schematic/ layout editor, Cadence ADE, Mentor Graphics Calibre DRC and LVS and PEX

TEACHING STAFF

• Assist.Prof. Mustafa AKTANCOORDINATOR
• Assist.Prof. Mustafa AKTAN