EMBEDDED SYSTEMS

AIM

Mastering the hardware description language, Verilog HDL, for the design (specification, simulation, and synthesis) of digital systems and implementing them on FPGAs.

CONTENT

This course contains; Digital Systems Review,FPGA Systems,Digital System Modelling using Verilog,Verilog Modelling Styles: Structural,Verilog Modelling Styles: Dataflow,Verilog Modelling Styles: Behavioral,Design verification,Combinational circuit design using Verilog,Sequential circuit design using Verilog,Finite State Machine Design using Verilog,CPU Design,Synthesis,Implementation of Verilog design on FPGA,Design Optimization.

1. 1

   Structural, dataflow, and behavioral Modelling of digital blocks using Verilog HDL

   Taught by: Discussion Method, Problem Solving Method, Self Study Method, Question - Answer Technique, Experimental Technique, Brainstorming Technique, Project Based Learning Model, Simulation Technique, Cooperative Learning, Experiential Learning, Lecture Method · Assessed by: Traditional Written Exam, Homework, Project Task

2. 2

   Modelling, simulating, and testing combinational circuits in Verilog

   Taught by: Discussion Method, Problem Solving Method, Self Study Method, Question - Answer Technique, Experimental Technique, Brainstorming Technique, Project Based Learning Model, Simulation Technique, Cooperative Learning, Experiential Learning, Lecture Method · Assessed by: Traditional Written Exam, Homework, Project Task

3. 3

   Modelling, simulating, and testing sequential circuits in Verilog

   Taught by: Discussion Method, Problem Solving Method, Self Study Method, Question - Answer Technique, Experimental Technique, Brainstorming Technique, Project Based Learning Model, Simulation Technique, Cooperative Learning, Experiential Learning, Lecture Method · Assessed by: Traditional Written Exam, Homework, Project Task

4. 4

   Digital System Synthesis for FPGA

   Taught by: Discussion Method, Problem Solving Method, Self Study Method, Question - Answer Technique, Experimental Technique, Brainstorming Technique, Project Based Learning Model, Simulation Technique, Cooperative Learning, Experiential Learning, Lecture Method · Assessed by: Traditional Written Exam, Homework, Project Task

5. 5

   Digital System Optimization for FPGA

   Taught by: Discussion Method, Problem Solving Method, Self Study Method, Question - Answer Technique, Experimental Technique, Brainstorming Technique, Project Based Learning Model, Simulation Technique, Cooperative Learning, Experiential Learning, Lecture Method · Assessed by: Traditional Written Exam, Homework, Project Task

WEEKLY PLAN

1. WEEK 1

   Digital Systems Review

   Preparation: Read the book

2. WEEK 2

   FPGA Systems

   Preparation: Read the book

3. WEEK 3

   Digital System Modelling using Verilog

   Preparation: Read the book

4. WEEK 4

   Verilog Modelling Styles: Structural

   Preparation: Read the book

5. WEEK 5

   Verilog Modelling Styles: Dataflow

   Preparation: Read the book

6. WEEK 6

   Verilog Modelling Styles: Behavioral

   Preparation: Read the book

7. WEEK 7

   Design verification

   Preparation: Read the book

8. WEEK 8

   Combinational circuit design using Verilog

   Preparation: Read the book

9. WEEK 9

   Sequential circuit design using Verilog

   Preparation: Read the book

10. WEEK 10

    Finite State Machine Design using Verilog

    Preparation: Read the book

11. WEEK 11

    CPU Design

    Preparation: Read the book

12. WEEK 12

    Synthesis

    Preparation: Read the book

13. WEEK 13

    Implementation of Verilog design on FPGA

    Preparation: Read the book

14. WEEK 14

    Design Optimization

    Preparation: Read the book

ASSESSMENT

• Rate of Midterm Exam to Success30%
• Rate of Final Exam to Success70%

WORKLOAD

READING

• Mano, Ciletti: Digital Design with an Introduction to the Verilog HDL, VHDL, and System Verilog, 6E Thomas, Moorby: The Verilog Hardware Description Language

TEACHING STAFF

• Assist.Prof. Mustafa AKTANCOORDINATOR
• Assist.Prof. Mustafa AKTAN